Stack package

ABSTRACT

A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads to of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean patent applicationnumber 10-2010-0010105 filed on Feb. 3, 2010, which is incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates generally to a stack package, to and moreparticularly, to a stack package in which a capacitor is embedded toreduce power noise.

A semiconductor package having a semiconductor chip capable of storingand/or processing a huge amount of data within a short period has beendeveloped.

It is known that stack a package, in which a plurality of semiconductorchips are stacked, increases data storage capacity. Further, a stackpackage is known, in which a memory semiconductor chip and a systemsemiconductor chip are stacked to increase a data storage capacity andalso to improve a data processing speed.

In order to maintain a data processing speed at a high level, it isnecessary to minimize power noise that is generated at an operatingfrequency of a semiconductor chip.

In general, reduction of power noise at a package level is effectivelyaccomplished by decreasing an inductance component. One exemplary methodof decreasing the inductance component at the package level, includes adecoupling capacitor disposed between a power pad and a ground pad.

Such a capacitor is often formed on the surface of a semiconductor chip,or formed as an embedded capacitor, which is embedded in a substrate.

Known methods of forming such a capacitor are costly and are unreliable.

Further, according to the known methods, it is difficult to realize acapacitor having a large capacity, and therefore such capacitors havelimitations in reducing power noise.

In addition, in the case of mounting the capacitor on the substrate, aproblem is caused in that the volume of a package increases and aseparate mounting process is needed.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the present invention include a stack package in which acapacitor for reducing power noise is reliably embedded at a reducedcost.

Also, embodiments of the present invention include a stack package whichcan realize a capacitor of a large capacity.

Further, embodiments of the present invention include a stack packagewhich can prevent the volume of the package from increasing andaccomplish the simplification of manufacturing processes.

In one embodiment of the present invention, a stack package comprises afirst semiconductor chip having a first surface on which first pads andsecond pads are disposed and a second surface which faces away from thefirst surface; a second semiconductor chip having a third surface whichfaces the first surface of the first semiconductor chip and on whichthird pads and fourth pads electrically connected with the second padsare disposed, and a fourth surface which faces away from the thirdsurface; and capacitors interposed between the first semiconductor chipand the second semiconductor chip, and having first electrodes which areelectrically connected with the first pads of the first semiconductorchip, second electrodes which are electrically is connected with thethird pads of the second semiconductor chip, and dielectrics which areinterposed between the first electrodes and the second electrodes.

The stack package may further comprise first connection memberselectrically connecting the second pads of the first semiconductor chipand the fourth pads of the second semiconductor chip.

The first pads may comprise power pads and the third pads may compriseground pads, or the first pads may comprise ground pads and the thirdpads may comprise power pads.

The first electrodes of the capacitors may be electrically connectedwith the first pads of the first semiconductor chip by the medium ofsecond connection members, and the second electrodes of the capacitorsmay be electrically connected with the third pads of the secondsemiconductor chip by the medium of third connection members.

The first electrodes and the second electrodes of the capacitors may bedisposed to directly contact the first surface of the firstsemiconductor chip including the first pads and the third surface of thesecond semiconductor chip including the third pads, respectively.

The first electrodes and the second electrodes of the capacitors mayhave a plate-like shape.

The first electrode of each capacitor may include a first is plate partand a plurality of first projecting parts which are formed on the firstplate part to extend toward the second electrode, and the secondelectrode of each capacitor may include a second plate part and aplurality of second projecting parts which are formed on the secondplate part to be placed between the first projecting parts.

Each capacitor including the first electrode, the second electrode andthe dielectric may have an area that is less than that of each of thefirst and second semiconductor chips.

The dielectrics of the capacitors may be disposed only between the firstelectrodes and the second electrodes.

The dielectrics of the capacitors may be disposed in a space between thefirst semiconductor chip and the second semiconductor chip, includingspaces between the first electrodes and the second electrodes.

Each of the capacitors may have an area that is the same as that of eachof the first and second semiconductor chips and may be defined with anopening through which a connection part between the second pad of thefirst semiconductor chip and the fourth pad of the second semiconductorchip passes.

The stack package may further comprise first redistribution linesdisposed on the third surface of the second semiconductor chip such thatone ends thereof are electrically connected with the third pads and theother ends thereof extend to a first edge of the third surface; andsecond redistribution lines disposed on the third is surface of thesecond semiconductor chip such that one ends thereof are electricallyconnected with the fourth pads and the other ends thereof extend to asecond edge of the third surface which is opposite the first edge.

The stack package may further comprise a substrate having a fifthsurface to which the fourth surface of the second semiconductor chip isattached and on which first connection pads connected with the firstredistribution lines and second connection pads connected with thesecond redistribution lines are disposed, and a sixth surface whichfaces away from the fifth surface and on which third connection pads aredisposed; connection members connecting the other ends of the firstredistribution lines with the first connection pads and the other endsof the second redistribution lines with the second connection pads; anencapsulant sealing the fifth surface of the substrate including thefirst and second semiconductor chips and the connection members; andexternal mounting members attached to the third connection members ofthe substrate.

The stack package may further comprise through-electrodes formed in thesecond semiconductor chip to pass through the third and fourth surfacesof the second semiconductor chip, and connected with the third pads andthe fourth pads.

The stack package may further comprise a substrate having a fifthsurface to which the fourth surface of the second is semiconductor chipis attached and on which first connection pads and second connectionpads connected with the through-electrodes are disposed, and a sixthsurface which faces away from the fifth surface and on which thirdconnection pads are disposed; an encapsulant sealing the fifth surfaceof the substrate including the first and second semiconductor chips; andexternal mounting members attached to the third connection pads of thesubstrate.

According to another embodiment of the present invention, a stackpackage comprises a first semiconductor chip having a first surface onwhich first pads and second pads are disposed and a second surface whichfaces away from the first surface; a second semiconductor chip having athird surface which faces the first surface of the first semiconductorchip and on which third pads and fourth pads electrically connected withthe second pads are disposed, and a fourth surface which faces away fromthe third surface; connection members electrically connecting the firstpads with the third pads and the second pads with the fourth pads; asubstrate having a fifth surface to which the fourth surface of thesecond semiconductor chip is attached and on which first connection padsand second connection pads are disposed, and a sixth surface which facesaway from the fifth surface and on which third connection pads aredisposed; capacitors having first electrodes which are electricallyconnected with the third pads, second electrodes which are connectedwith the first connection pads, and dielectrics interposed between thefirst electrodes and second electrodes; and connection membersconnecting the fourth pads of the second semiconductor chip with thesecond connection pads of the substrate.

The stack package may further comprise first redistribution linesdisposed on the third surface of the second semiconductor chip such thatone ends thereof are electrically connected with the third pads and theother ends thereof extend to a first edge of the third surface, to beconnected with the first electrodes of the capacitors; and secondredistribution lines disposed on the third surface of the secondsemiconductor chip such that one ends thereof are electrically connectedwith the fourth pads and the other ends thereof extend to a second edgeof the third surface which is opposite the first edge, to be connectedwith the second connection pads of the substrate.

The stack package may further comprise an encapsulant sealing the fifthsurface of the substrate including the first and second semiconductorchips and the capacitors; and external mounting members attached to thethird connection members of the substrate.

According to another embodiment of the present invention, a stackpackage comprises a first semiconductor chip having a first surface onwhich first pads and second pads are disposed and a second surface whichfaces away from the first surface; a second is semiconductor chip havinga third surface which faces the first surface of the first semiconductorchip and on which third pads and fourth pads electrically connected withthe second pads are disposed, and a fourth surface which faces away fromthe third surface; first redistribution lines disposed on the thirdsurface of the second semiconductor chip, and having one ends which areconnected with the first pads and the third pads and the other endswhich extend to a first side surface meeting the third surface; secondredistribution lines disposed on the third surface of the secondsemiconductor chip, and having one ends which are connected with thesecond pads and the fourth pads and the other ends which extend to asecond side surface facing away from the first side surface; a substratehaving a fifth surface to which the fourth surface of the secondsemiconductor chip is attached and on which first connection pads andsecond connection pads are disposed, and a sixth surface which facesaway from the fifth surface and on which third connection pads aredisposed; capacitors having first electrodes which are connected withthe other ends of the first redistribution lines extending to the firstside surface of the second semiconductor chip, second electrodes whichare connected with the first connection pads, and dielectrics which areinterposed between the first electrodes and the second electrodes; andconnection members connecting the other ends of the secondredistribution lines and the second connection pads of the substrate.

The first and second redistribution lines may directly contact the firstand third pads and the second and fourth pads, and may be electricallyinsulated from the first and second semiconductor chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are cross-sectional views showing a stack package inaccordance with an embodiment of the present invention.

FIGS. 3 through 7 are cross-sectional views showing a capacitor of thestack package in accordance with an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a stack package in accordancewith an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a stack package in accordancewith an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a stack package in accordancewith an embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

In the present invention, when realizing a stack package of achip-on-chip structure, power pads and ground pads of an uppersemiconductor chip and a lower semiconductor chip are connected bycapacitors.

Therefore, according to embodiments of the present invention, eventhough the capacitors are embedded, the capacitors can be relativelysimply formed, costs can be saved, and reliability can be secured.

Also, in the present invention, by freely adjusting the area of theelectrodes of the capacitors, capacitors of a large capacityadvantageous to the reduction of power noise can be easily realized.

Further, in the present invention, because the capacitors are disposedbetween the upper semiconductor chip and the lower semiconductor chip,the volume of the entire stack package is not unnecessarily increased.

Hereafter, specific embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings.

It is to be understood herein that the drawings are not necessarily toscale and in some instances proportions may have been exaggerated inorder to more clearly depict certain features of the invention.

FIGS. 1 and 2 are cross-sectional views showing a stack package inaccordance with an embodiment of the present invention.

Referring to FIG. 1, a stack package 100 in accordance with anembodiment of the present invention includes a first semiconductor chip110, a second semiconductor chip 120, and capacitors 130 connected tothe first semiconductor chip 110 and the second semiconductor chip 120.

The first semiconductor chip 110 has a first surface S1 on which firstpads 112 and second pads 114 are disposed and a second surface S2 whichfaces away from the first surface S1. The second semiconductor chip 120has a third surface S3 on which third pads 122 and fourth pads 124 aredisposed and a fourth surface S4 which faces away from the third surfaceS3. As shown in FIG. 1, the first semiconductor chip 110 and the secondsemiconductor chip 120 are oppositely positioned. That is, for example,the first semiconductor chip 110 is positioned above the secondsemiconductor chip 120, and the first surface S1 of the firstsemiconductor 110 faces the third surface S3 of the second semiconductorchip 120.

For example, the first pads 112 of the first semiconductor chip 110 arepower pads, and the third pads 122 of the second semiconductor chip 120,which correspond to the first pads 112 of the first semiconductor chip110, are ground pads. Alternatively, the first pads 112 of the firstsemiconductor chip 110 may be ground pads, and the third pads 122 of thesecond semiconductor chip 120, which correspond to the first pads 112 ofthe first semiconductor chip 110, may be power pads. Both the secondpads 114 of the first semiconductor chip 110 and the fourth pads 124 ofthe second semiconductor chip 120 are signal pads.

It should be understood, that while not shown in a drawing, each of thefirst semiconductor chip 110 and the second is semiconductor chip 120has therein a circuit unit, which includes a data storage section forstoring data and a data processing section for processing data.

The third pads 122 of the second semiconductor chip 120 can be disposedat positions which face the first pads 112 of the first semiconductorchip 110 as shown in FIG. 1. Of course, while not shown in a drawing, itis conceivable that the third pads 122 of the second semiconductor chip120 can be disposed at positions which do not face the first pads 112 ofthe first semiconductor chip 110.

The second pads 114 of the first semiconductor chip 110 and thecorresponding fourth pads 124 of the second semiconductor chip 120 areelectrically connected with each other through first connection members142. The first connection members 142 may comprise an electricallyconductive material, for example, solders or bumps.

Each capacitor 130 includes a first electrode 132 electrically connectedwith the first pad 112 of the first semiconductor chip 110, a secondelectrode 134 electrically connected with the third pad 122 of thesecond semiconductor chip 120, and a dielectric 136 interposed betweenthe first electrode 132 and the second electrode 134.

The first electrode 132 is electrically connected with the first pad 112of the first semiconductor chip 110 through a second is connectionmember 144, and the second electrode 134 is electrically connected withthe third pad 122 of the second semiconductor chip 120 through a thirdconnection member 146. The second and third connection members 144 and146 may comprise an electrically conductive material, for examplesolders or bumps.

In the embodiment, a surface of the capacitor 130 has an area that isless than an area of the surfaces S1, S3 of the first and secondsemiconductor chips 110 and 120, respectively.

However, as shown in FIG. 3, a surface of the capacitor 130 can have anarea as great as the area of each of the surfaces S1, S3 first andsecond semiconductor chips 110 and 120, respectively, in order to securean increased capacity. In this case as shown in FIG. 3, the capacitor130 has an opening v through which a connection part between the secondpad 114 of the first semiconductor chip 110 and the fourth pad 124 ofthe second semiconductor chip 120 passes. In detail, the first electrode132, the second electrode 134 and the dielectric 136 of the capacitor130 are formed so as to have defined therein the opening v through whichthe first connection member 142 connecting the second pad 114 of thefirst semiconductor chip 110 and the fourth pad 124 of the secondsemiconductor chip 120 passes.

In the embodiment shown in FIG. 3, the first electrode 132 and thesecond electrode 134 of the capacitor 130 are connected with the firstpad 112 of the first semiconductor chip 110 and the third pad 122 of thesecond semiconductor chip 120 through the second connection member 144and the third connection member 146, respectively.

As shown in FIG. 4, the first electrode 132 and the second electrode 134of the capacitor 130 can be formed so as to directly contact the firstsurface S1 of the first semiconductor chip 110 including the first pad112 and the third surface S3 of the second semiconductor chip 120including the third pad 122, respectively.

As shown in FIG. 4, a surface of the capacitor 130, which includes thefirst electrode 132 and the second electrode 134 formed to directlycontact the first surface S1 of the first semiconductor chip 110 and thethird surface S3 of the second semiconductor chip 120, can have an areathat is less than the area of surfaces S1 and S3 of the first and secondsemiconductor chips 110 and 120, respectively, as shown in FIG. 4, orcan have an area that is the same as the area of the surfaces S1 and S3of the first and second semiconductor chips 110 and 120, respectively,as shown in FIG. 5, in order to secure an increased capacity. In thelatter case as shown in FIG. 5, the capacitor 130 has an opening vthrough which the first connection member 142 connecting the second pad114 of the first semiconductor chip 110 and the fourth pad 124 of thesecond semiconductor chip 120 passes.

In addition, in the embodiment, each of the first electrode 132 and thesecond electrode 134 of the capacitor 130 is formed to have a plate-likeshape as shown in FIGS. 1 through 5.

As shown in FIG. 6, in order to secure an increased capacity, the firstelectrode 132 can be formed to have a first plate part 132 a and aplurality of first projecting parts 132 b formed on the first plate part132 a so as to project toward the second electrode 134, and the secondelectrode 134 can be formed to have a second plate part 134 a and aplurality of second projecting parts 134 b formed on the second platepart 134 a so as to be respectively placed between the first projectingparts 132 b.

A surface of the capacitor 130, which includes the first electrode 132having the first plate part 132 a and the first projecting parts 132 band the second electrode 134 having the second plate part 134 a and thesecond projecting parts 134 b, can be formed to have an area that isless than the area of each of the surfaces S1 and S3 of the first andsecond semiconductor chips 110 and 120, respectively, as shown in FIG.6, or can be formed to have an area that is the same as the area of eachof the surfaces S1 and S3 of the first and second semiconductor chips110 and 120, as shown in FIG. 7. In the latter case, the capacitor 130has an opening v through which the first connection member 142connecting the second pad 114 of the first semiconductor chip 110 andthe fourth pad 124 of the second semiconductor chip 120 passes.

In the case of the stack package structures shown in FIGS. 6 and 7, thespace between the first semiconductor chip 110 and the secondsemiconductor chip 120 is filled with the dielectric 136 of thecapacitor 130, therefore it is not necessary to fill a separateunderfill in the space between the first semiconductor chip 110 and thesecond semiconductor chip 120, and an underfill omission effect can beachieved.

In addition, while it is illustrated and described in the embodimentthat the third pads 122 of the second semiconductor chip 120 aredisposed on the third surface S3 of the second semiconductor chip 120 insuch a way as to respectively face the first pads 112 of the firstsemiconductor chip 110, it is conceivable that the third pads 122 of thesecond semiconductor chip 120 can be disposed on the third surface S3 ofthe second semiconductor chip 120 at positions which do not face thefirst pads 112 of the first semiconductor chip 110. In this case, it canbe understood that the shape of the capacitors 130 is changedaccordingly.

Referring to FIG. 2, the stack package 100 can include firstredistribution lines 126 and second redistribution lines 128 which areformed on the third surface S3 of the second semiconductor chip 120.Each first redistribution line 126 is disposed on the third surface S3of the second semiconductor chip 120 such that one end thereof iselectrically connected with the third pad 122 and the second end thereofextends to an edge of the third surface S3. Each second redistributionline 128 is disposed on the third surface S3 of the second semiconductorchip 120 such that one end thereof is electrically connected with thefourth pad 124 and the second end thereof extends to a second edge ofthe third surface S3 which is opposite the first edge. The first andsecond redistribution lines 126 and 128 facilitate easy electricalconnection with a substrate, which will be described below.

The stack package 100 as shown in FIG. 2, can further includes asubstrate 160 having an upper surface on which the second semiconductorchip 120 is attached, connection members 172 and 174 which connect theredistribution lines 126 and 128 with the substrate 160, and anencapsulant 180 sealing the first and second semiconductor chips 110 and120 and the connection members 172 and 174, and external mountingmembers 190 which are attached to the substrate 160.

The substrate 160 has a fifth surface S5 to which the fourth surface S4of the second semiconductor chip 120 is attached and on which firstconnection pads 162 and second connection pads 164 are disposed, and asixth surface S6 which faces away from the fifth surface S5 and on whichthird connection pads 166 are disposed. For example, the substrate 160may comprise a printed circuit board.

The first connection pads 162 are disposed on portions of the fifthsurface S5 of the substrate 160 which are adjacent to the second of thefirst redistribution lines 126, and are electrically connected with thefirst redistribution lines 126 through the first connection members 172.The second connection pads 164 are disposed on portions of the fifthsurface S5 of the substrate 160 which at the second ends of the secondredistribution lines 128, and are electrically connected with the secondredistribution lines 128 through the second connection members 174.

The first connection members 172 and the second connection members 174preferably comprise conductive wires, or may comprise a conductive inkor a pattern film. The encapsulant 180 preferably comprises an epoxymolding compound (EMC), or may comprise other insulation materials. Theexternal mounting members 190 preferably comprise solder balls, or maycomprise conductive pins or a solder paste.

Since the stack package according to an embodiment has a structure inwhich the capacitors are connected to the power pads of the firstsemiconductor chip and the grounds pads of the second semiconductorchip, the capacitors are can be easily formed, and the reliability ofthe capacitors can be improved.

Also, since the stack package has a structure in which the capacitorsare disposed between the first semiconductor chip and the secondsemiconductor chip, the volume of the package is not unnecessarilyincreased, and a separate process for mounting capacitors is not needed.

Further, the capacitors can have a large capacity since sectional shapeof the capacitor electrodes can be optionally changed as describedabove, and accordingly, power noise reducing effect can be improved.

FIG. 8 is a cross-sectional view showing an exemplary stack package. Thesame reference numerals will be used to refer to the same componentelements as those shown in FIG. 2, and the detailed descriptions of thesame component elements will be omitted herein.

Referring to FIG. 8, a stack package 200 includes first and secondthrough-electrodes 152 and 154 formed within a second semiconductor chip120. The first and second through-electrodes 152 and 154 are formed soas to pass through a third surface S3 and a fourth surface S4 of thesecond semiconductor chip 120 and be connected with third pads 122 andfourth pads 124, respectively. Preferably, the first and secondthrough-electrodes 152 and 154 are electrically insulated from the bodyof the second semiconductor chip 120.

The stack package 200 as shown in FIG. 8 further includes a substrate160 and connection members 162 and 164. The positions of the connectionmembers 162 and 164 are changed when compared to those of the firstembodiment. The substrate 160 may comprise a printed circuit board. Thesubstrate 160 has a fifth surface S5 to which the fourth surface S4 ofthe second semiconductor chip 120 is attached and on which firstconnection pads 162 and second connection pads 164 are disposed, and asixth surface S6 which faces away from the fifth surface S5 and on whichthird connection pads 166 are disposed. The first connection pads 162and the second connection pads 164 are respectively connected with thefirst through-electrodes 152 and the second through-electrodes 154, aswill be described below in detail.

The stack package 200 as shown in FIG. 8 further includes an encapsulant180 sealing the fifth surface S5 of the substrate 160 and the first andsecond semiconductor chip 110 and 120, and includes external mountingmembers 190, which are attached to the third connection pads 166 of thesubstrate 160. The external mounting members 190 preferably comprisesolder balls, or may comprise conductive pins or a solder paste.

The stack package 200 as shown in FIG. 8 further includes capacitors 130constructed so as to be connected with the first and secondsemiconductor chips 110 and 120. Each capacitor 130 includes a firstelectrode 132 electrically connected with each first pad 112 of thefirst semiconductor chip 110 through a second connection member 144, asecond electrode 134 electrically connected with each third pad 122 ofthe second semiconductor chip 120 through a third connection member 146,and a dielectric 136 interposed between the first electrode 132 and thesecond electrode 134.

While it is shown FIG. 8 in that a surface of the capacitor 130 has anarea that is less than the area of each of the surfaces S1 and S3 of thefirst and second semiconductor chips 110 and 120, respectively, it canbe envisaged that a surface of the capacitor 130 can have an area thatis the same as the area of each of the surfaces S1 and S3 of the firstand second semiconductor chips 110 and 120, respectively, as shown inFIG. 3, so as to secure a large capacity. In this case, the capacitor130 has an opening v through which the first connection member 142connecting the second pad 114 of the first semiconductor chip 110 andthe fourth pad 124 of the second semiconductor chip 120 passes.

Also, while it is shown in FIG. 8 that the first and second electrodes132 and 134 of the capacitor 130 are formed to be respectively connectedwith the first pad 112 of the first semiconductor chip 110 and the thirdpad 122 of the second semiconductor chip 120 through the second andthird connection members 144 and 146, it can be contemplated that thefirst electrode 132 and the second electrode 134 of the capacitor 130can be formed in such a way as to directly contact the first surface S1of the first semiconductor chip 110 including the first pad 112 and thethird surface S3 of the second semiconductor chip 120 including thethird pad 122, respectively, as shown in FIGS. 4 and 5.

Moreover, while it is shown in FIG. 8 that each of the first and secondelectrodes 132 and 134 of the capacitor 130 has a plate-like shape, itis conceivable that the first electrode 132 can be formed to have afirst plate part and first projecting parts and the second electrode 134can be formed to have a second plate part and second projecting parts asshown in FIGS. 6 and 7, in order to secure a large capacity.

Here, the capacitor 130, which includes the first electrode 132 havingthe first plate part and the first projecting parts, the secondelectrode 134 having the second plate part and the second projectingparts, and the dielectric 136 interposed between the first electrode 132and the second electrode 134, can be formed such that an area of asurface of the capacitor 130 is less than that of each of the surfacesS1 and S3 of the first and second semiconductor chips 110 and 120,respectively, as shown in FIG. 6, or can be formed such that an area ofa surface of the capacitor 130 is the same as that of each of the firstand second semiconductor chips 110 and 120, as shown in FIG. 7.

FIG. 9 is a cross-sectional view showing an exemplary stack package. Thesame reference numerals will be used to refer to the same componentelements as those shown in FIG. 2, and the detailed descriptions of thesame component elements will be omitted herein.

Referring to FIG. 9, a stack package 300 includes capacitors 130 whichare formed between a second semiconductor chip 120 and a substrate 160.In detail, each capacitor 130 includes a first electrode 132 which isconnected to a third pad 122 of a second semiconductor chip 120, asecond electrode 134 which is connected to a first connection pad 162 ofa substrate 160, and a dielectric 136 which is interposed between thefirst electrode 132 and the second electrode 134.

The first electrode 132 is connected with the second of a firstredistribution line 126 formed on a third surface S3 of the secondsemiconductor chip 120, where one end of the first redistribution line126 is connected with the third pad 122 and the second end extending tothe first edge of the third surface S3. Therefore, it can be understoodthat the first electrode 132 is electrically connected with the thirdpad 122 of the second semiconductor chip 120 through the firstredistribution line 126.

The dielectric 136 of the capacitor 130 is not limited to the shape asshown in FIG. 8 and can be formed to have various shapes according todifferent manufacturing processes.

In the stack package 300, a second pad 114 disposed on a first surfaceS1 of a first semiconductor chip 110 and a fourth pad 124 disposed onthe third surface S3 of the second semiconductor chip 120 areelectrically connected with each other through a first connection member142, and a first pad 112 disposed on the first surface S1 of the firstsemiconductor chip 110 and the third pad 122 disposed on the thirdsurface S3 of the second semiconductor chip 120 are electricallyconnected with each other through a fourth connection member 148. Thefirst and fourth connection members 142 and 148 may comprise, forexample, a conductive material such as solders or bumps.

In the stack package 300, a second redistribution line 128 is formed onthe third surface S3 of the second semiconductor chip 120 such that oneend thereof is electrically connected with the fourth pad 124 and asecond end extends to the second edge of the third surface S3 which isopposite the first edge. The second of the second redistribution line128 is connected with a second connection pad 164 which is disposed on afifth surface S5 of the substrate 160, through a connection member 176.

Further, in the stack package 300, the fifth surface S5 of the substrate160, the first and second semiconductor chips 110 and 120, and thecapacitors 130 are sealed by an encapsulant 180 such as an EMC. Externalmounting members 190 such as solder balls are attached to thirdconnection pads 166 disposed on a sixth surface S6 of the substrate 160facing away from the fifth surface S5.

FIG. 10 is a cross-sectional view illustrating an exemplary stackpackage. The same reference numerals will be used to refer to the samecomponent elements as those shown in FIG. 2, and the detaileddescriptions of the same component elements will be omitted herein.

Referring to FIG. 10, a stack package 400 includes first and secondsemiconductor chips 110 and 120 which are oppositely positioned, asubstrate 160 to which a fourth surface S4 of the second semiconductorchip 120 is attached, and capacitors 130 which are formed between thesecond semiconductor chip 120 and the substrate 160.

The stack package 400 further includes first redistribution lines 126and second redistribution lines 128 which are interposed between thefirst semiconductor chip 110 and the second semiconductor chip 120.

Each first redistribution line 126 is formed on a third surface S3 ofthe second semiconductor chip 120 such that a first end thereof isconnected with a first pad 112 of the first semiconductor chip 110 and athird pad 122 of the second semiconductor chip 120 and a second endthereof extends to a first side surface adjoining the third surface S3.Each second redistribution line 128 is formed on the third surface S3 ofthe second semiconductor chip 120 such that a first end thereof isconnected with a second pad 114 of the first semiconductor chip 110 anda fourth pad 124 of the second semiconductor chip 120 and a second endthereof extends to a second side surface adjoining the third surface S3and facing away from the first side surface. The first and secondredistribution lines 126 and 128 are disposed to directly contact both afirst surface S1 of the first semiconductor chip 110, including firstpads 112, and the third surface S3 of the second semiconductor chip 120,including third pads 122, and the first surface S1 of the firstsemiconductor chip 110, including second pads 114, and the third surfaceS3 of the second semiconductor chip 120, including fourth pads 124,respectively. The first and second redistribution lines 126 and 128 areelectrically insulated from the bodies of the first and secondsemiconductor chips 110 and 120.

The substrate 160 has a fifth surface S5 to which the fourth surface S4of the second semiconductor chip 120 is attached and on which first andsecond connection pads 162 and 164 are disposed, and a sixth surface S6facing away from the fifth surface S5 on which third connection pads 166are disposed. The first connection pads 162 are disposed on portions ofthe fifth surface S5 of the substrate 160 adjacent to the first sidesurface of the second semiconductor chip 120, and the second connectionpads 164 are disposed on portions of the fifth surface S5 of thesubstrate 160 adjacent to the second side surface of the secondsemiconductor chip 120.

Each capacitor 130 includes a first electrode 132 connected with thethird pad 122 of the second semiconductor chip 120, a second electrode134 connected with the first connection pad 162 of the substrate 160,and a dielectric 136 interposed between the first electrode 132 and thesecond electrode 134. In detail, the first electrode 132 is formed to beconnected with the second end of the first redistribution line 126 whichhas the first end thereof connected with the third pad 122 of the secondsemiconductor chip 120 and the second end thereof disposed on the firstside surface of the second semiconductor chip 120. Therefore, it can beunderstood that the first electrode 132 is electrically connected withthe third pad 122 of the second semiconductor chip 120 through the firstredistribution line 126.

The dielectric 136 of the capacitor 130 can be formed to have variousshapes in addition to the shape shown in the drawing.

The stack package 400 further includes connection members 178 connectingthe second ends of the second redistribution lines 128 disposed on thesecond side surface with second connection pads 164 of the substrate160, external mounting members 190 attached to third connection pads 166disposed on the sixth surface S6 of the substrate 160, and anencapsulant 180 sealing the fifth surface S5 of the substrate 160, thefirst and second semiconductor chips 110 and 120, and the capacitors130. The connection members 178 can comprise a conductive material suchas solders, and the encapsulant 180 can comprise, for example, an EMC.The external mounting members 190 preferably comprise solder balls, orcan comprise conductive pins or a solder paste.

In the stack package 400, in the case where the first connection pads162 of the substrate 160, to which the second is electrodes 134 of thecapacitors 130 are connected, comprise power pads, the first and thirdpads 112 and 122 of the first and second semiconductor chips 110 and120, which are connected to the first electrodes 132 of the capacitors130 through the first redistribution lines 126, comprise power pads.Alternatively, in the case where the first connection pads 162 of thesubstrate 160, to which the second electrodes 134 of the capacitors 130are connected, comprise ground pads, the first and third pads 112 and122 of the first and second semiconductor chips 110 and 120, which areconnected to the first electrodes 132 of the capacitors 130 through thefirst redistribution lines 126, comprise ground pads.

As is apparent from the above description, the stack package accordingto the present invention provides advantages in that, since the stackpackage has a structure in which decoupling capacitors are disposedbetween power pads and ground pads at a package level, power noise canbe effectively reduced through the reduction of an inductance component,and accordingly, a desired data processing speed can be maintained.

Although specific embodiments of the present invention to have beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and the spirit of theinvention as disclosed in the accompanying claims.

1. A stack package comprising: a first semiconductor chip including afirst surface having first pads and second pads disposed thereon, and asecond surface facing away from the first surface; a secondsemiconductor chip including a third surface having third pads andfourth pads disposed thereon, and a fourth surface facing away from thethird surface, wherein the third surface of the second semiconductorchip faces the first surface of the first semiconductor chip and thefourth pads are electrically connected with the second pads; andcapacitors interposed between the first semiconductor chip and thesecond semiconductor chip, and having first electrodes electricallyconnected with the first pads of the first semiconductor chip, secondelectrodes electrically connected with the third pads of the secondsemiconductor chip, and dielectrics interposed between the firstelectrodes and the second electrodes.
 2. The stack package according toclaim 1, further comprising: first connection members electricallyconnecting the second pads of the first semiconductor chip and thefourth pads of the second semiconductor chip.
 3. The stack packageaccording to claim 1, wherein the first pads comprise power pads and thethird pads comprise ground pads, or the first pads comprise ground padsand the third pads comprise power pads.
 4. The stack package accordingto claim 1, wherein the first electrodes of the capacitors areelectrically connected with the first pads of the first semiconductorchip through second connection members, and the second electrodes of thecapacitors are electrically connected with the third pads of the secondsemiconductor chip through third connection members.
 5. The stackpackage according to claim 1, wherein the first electrodes and thesecond electrodes of the capacitors directly contact the first surfaceof the first semiconductor chip having the first pads disposed thereonand the third surface of the second semiconductor chip having the thirdpads disposed thereon, respectively.
 6. The stack package according toclaim 1, wherein the first electrodes and the second electrodes of thecapacitors have a shape of a plate.
 7. The stack package according toclaim 1, wherein the first electrode of each capacitor includes a firstplate part having a plurality of first projecting parts formed thereonextending toward the second electrode, and the second electrode of eachcapacitor includes a second plate part having a plurality of secondprojecting parts formed thereon so as to extend toward the firstelectrode between the first projecting parts.
 8. The stack packageaccording to claim 1, wherein an area of a surface of each capacitor isless than an area of each of the first surface of the firstsemiconductor chip and an area of the third surface of the secondsemiconductor chip.
 9. The stack package according to claim 8, whereinthe dielectrics of the capacitors are disposed only between the firstelectrodes and the second electrodes.
 10. The stack package according toclaim 8, wherein the dielectrics of the capacitors are disposed in aspace between the first semiconductor chip and the second semiconductorchip, including spaces between the first electrodes and the secondelectrodes.
 11. The stack package according to claim 1, wherein an areaof a surface of each of the capacitors is the substantially equal to anarea of each of the first surface of the first semiconductor chip and anarea of the third surface of the second semiconductor chips, and anopening is defined in each of the capacitors through which a connectionpart connecting the second pad of the first semiconductor chip and thefourth pad of the second semiconductor chip passes.
 12. The stackpackage according to claim 1, further comprising: first redistributionlines disposed on the third surface of the second semiconductor chipincluding first ends electrically connected with the third pads andsecond ends extending to an edge of the third surface; and secondredistribution lines disposed on the third surface of the secondsemiconductor chip including first ends electrically connected with thefourth pads and the second ends extending to a second edge of the thirdsurface opposite the first edge.
 13. The stack package according toclaim 12, further comprising: a substrate having a fifth surfaceattached to the fourth surface of the second semiconductor chip andhaving disposed thereon first connection pads connected with the firstredistribution lines and second connection pads connected with thesecond redistribution lines, and a sixth surface facing away from thefifth surface and having third connection pads disposed thereon;connection members connecting the second ends of the firstredistribution lines with the first connection pads and the second endsof the second redistribution lines with the second connection pads; anencapsulant sealing the fifth surface of the substrate, the first andsecond semiconductor chips, and the connection members; and externalmounting members attached to the third connection members of thesubstrate.
 14. The stack package according to claim 1, furthercomprising: through-electrodes formed in the second semiconductor chippassing through the third and fourth surfaces of the secondsemiconductor chip, and connected with the third pads and the fourthpads.
 15. The stack package according to claim 14, further comprising: asubstrate having a fifth surface attached to the fourth surface of thesecond semiconductor chip and having disposed thereon first connectionpads and second connection pads connected with the through-electrodes,and a sixth surface facing away from the fifth surface having thirdconnection pads disposed thereon; an encapsulant sealing the fifthsurface of the substrate and the first and second semiconductor chips;and external mounting members attached to the third connection pads ofthe substrate.
 16. A stack package comprising: a first semiconductorchip including a first surface having first pads and second padsdisposed thereon, and a second surface facing away from the firstsurface; a second semiconductor chip including a third surface havingthird pads and fourth pads disposed thereon, and a fourth surface whichfacing away from the third surface, wherein the third surface of thesecond semiconductor chip faces the first surface of the firstsemiconductor chip and the fourth pads are electrically connected withthe second pads; connection members electrically connecting the firstpads with the third pads and the second pads with the fourth pads; asubstrate including a fifth surface attached to the fourth surface ofthe second semiconductor chip and having disposed thereon firstconnection pads and second connection pads, and a sixth surface facingaway from the fifth surface and having third connection pads disposedthereon; capacitors including first electrodes electrically connectedwith the third pads, second electrodes electrically connected with thefirst connection pads, and dielectrics interposed between the firstelectrodes and second electrodes; and connection members connecting thefourth pads of the second semiconductor chip with the second connectionpads of the substrate.
 17. The stack package according to claim 16,further comprising: first redistribution lines disposed on the thirdsurface of the second semiconductor chip having first ends electricallyconnected with the third pads and second ends extending to a first edgeof the third surface electrically connected with the first electrodes ofthe capacitors; and second redistribution lines disposed on the thirdsurface of the second semiconductor chip having first ends electricallyconnected with the fourth pads and second ends extending to a secondedge of the third surface opposite the first edge, the second endselectrically connected with the second connection pads of the substrate.18. The stack package according to claim 16, further comprising: anencapsulant sealing the fifth surface of the substrate, the first andsecond semiconductor chips, and the capacitors; and external mountingmembers attached to the third connection members of the substrate.
 19. Astack package comprising: a first semiconductor chip including a firstsurface having first pads and second pads disposed thereon, and a secondsurface facing away from the first surface; a second semiconductor chipincluding a third surface having third pads and fourth pads disposedthereon, and a fourth surface which facing away from the third surface,wherein the third surface of the second semiconductor chip faces thefirst surface of the first semiconductor chip and the fourth pads areelectrically connected with the second pads; first redistribution linesdisposed on the third surface of the second semiconductor chip havingfirst ends connected with the first pads and the third pads, and secondends extending to a first side surface adjoining the third surface;second redistribution lines disposed on the third surface of the secondsemiconductor chip having first ends connected with the second pads andthe fourth pads, and second ends extending to a second side surfaceadjoining the third surface, the second side surface facing away fromthe first side surface; a substrate including a fifth surface attachedto the fourth surface of the second semiconductor chip having firstconnection pads and second connection pads disposed thereon, and a sixthsurface facing away from the fifth surface having third connection padsdisposed thereon; capacitors including first electrodes connected withthe second ends of the first redistribution lines extending to the firstside surface of the second semiconductor chip, second electrodesconnected with the first connection pads, and dielectrics interposedbetween the first electrodes and the second electrodes; and connectionmembers connecting the second ends of the second redistribution linesand the second connection pads of the substrate.
 20. The stack packageaccording to claim 19, wherein the first redistribution lines directlycontact the first pads and third pads and the second redistributionlines directly contact the second pads and fourth pads, and the firstand second redistribution lines are electrically insulated from thefirst and second semiconductor chips.